View ATF1504ASV-15QC100_2375898.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? high-density, high-performance, electrically-erasable complex programmable logic device ? 3.0 to 3.6v operating range ? 64 macrocells ? 5 product terms per macrocell, expandable up to 40 per macrocell ? 44, 68, 84, 100 pins ? 15 ns maximum pin-to-pin delay ? registered operation up to 77 mhz ? enhanced routing resources in-system programmability (isp) via jtag flexible logic macrocell ? d/t/latch configurable flip-flops ? global and individual register control signals ? global and individual output enable ? programmable output slew rate ? programmable output open-collector option ? maximum logic utilization by burying a register with a com output advanced power management features ? automatic 5 a standby for ? l ? version ? pin-controlled 100 a standby mode (typical) ? programmable pin-keeper circuits on inputs and i/os ? reduced-power feature per macrocell available in commercial and industrial temperature ranges available in 44-, 68-, and 84-lead plcc; 44- and 100-lead tqfp; and 100-lead pqfp advanced ee technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20 year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing to ieee std. 1149.1-1990 and 1149.1a-1993 supported pci-compliant security fuse feature enhanced features improved connectivity (additional feedback routing, alternate input routing) output enable product terms transparent-latch mode combinatorial output with registered feedback within any macrocell three global clock pins itd (input transition detection) circuits on global clocks, inputs and i/o fast registered input from product term programmable ? pin-keeper ? option v cc power-up reset option pull-up option on jtag pins tms and tdi advanced power management features ? edge-controlled power-down ? l ? ? individual macrocell power option ? disable itd on global clocks, inputs and i/o low-voltage, complex programmable logic device atf1504asv atf1504asvl rev. 1409i ? pld ? 2/03
2 atf1504asv(l) 1409i ? pld ? 2/03 44-lead tqfp top view 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gclk2/oe2/i gclr/i i/oe1 gclk1/i gnd gclk3/i/o i/o 44-lead plcc top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gclk2/oe2/i gclr/i oe1/i gclk1/i gnd gclk3/i/o i/o 68-lead plcc top view 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 i/o vccio i/o/td1 i/o i/o i/o gnd i/o/pd1 i/o i/o/tms i/o vccio i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o vccio i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o i/o i/o i/o vccio i/o i/o gnd vccint i/o i/o/pd2 gnd i/o i/o i/o i/o vccio i/o i/o i/o gnd i/o i/o vccint gclk2/oe2/i gclr/i oe1/i gclk1/i gnd gclk3/i/o i/o vccio i/o i/o 84-lead plcc top view 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 i/o vccio i/o/tdi i/o i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o gnd i/o i/o i/o vccint gclk2/oe2/i i/gclr i/oe1 gclk1/i gnd gclk3/i/o i/o i/o vccio 1/o i/o i/o
3 atf1504asv(l) 1409i ? pld ? 2/03 100-lead pqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc nc i/o i/o vccio i/o/tdi nc i/o nc i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o nc i/o nc i/o gnd nc nc nc nc i/o i/o gnd i/o/tdo nc i/o nc i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o nc i/o nc i/o vccio nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o 100-lead tqfp top view nc nc vccio i/o/tdi nc i/o nc i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o nc i/o nc i/o i/o gnd i/o/tdo nc i/o nc i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o nc i/o nc i/o vccio gnd nc nc i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o nc nc i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o nc nc i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4 atf1504asv(l) 1409i ? pld ? 2/03 description the atf1504asv(l) is a high-performance, high-density complex programmable logic device (cpld) that utilizes atmel ? s proven electrically-erasable memory technology. with 64 logic macrocells and up to 68 inputs, it easily integrates logic from several ttl, ssi, msi, lsi and classic plds. the atf1504asv(l) ? s enhanced routing switch matri- ces increase usable gate count and the odds of successful pin-locked design modifications. the atf1504asv(l) has up to 68 bi-directional i/o pins and four dedicated input pins, depending on the type of device package selected. each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. each of the 64 macrocells generates a buried feedback that goes to the global bus. each input and i/o pin also feeds into the global bus. the switch matrix in each logic block then selects 40 individual signals from the global bus. each macrocell also gener- ates a foldback logic term that goes to a regional bus. cascade logic between macrocells in the atf1504asv(l) allows fast, efficient generation of complex logic func- tions. the atf1504asv(l) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. the atf1504asv(l) macrocell, shown in figure 1, is flexible enough to support highly- complex logic functions operating at high speed. the macrocell consists of five sections: product terms and product term select multiplexer, or/xor/cascade logic, a flip-flop, output select and enable, and logic array inputs.
5 atf1504asv(l) 1409i ? pld ? 2/03 block diagram unused product terms are automatically disabled by the compiler to decrease power consumption. a security fuse, when programmed, protects the contents of the atf1504asv(l). two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signa- ture is accessible regardless of the state of the security fuse. the atf1504asv(l) device is an in-system programmable (isp) device. it uses the industry-standard 4-pin jtag interface (ieee std. 1149.1), and is fully-compliant with jtag ? s boundary-scan description language (bsdl). isp allows the device to be pro- grammed without removing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. product terms and select mux each atf1504asv(l) macrocell has five product terms. each product term receives as its inputs all signals from both the global bus and regional bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is determined by the design compiler, which selects the optimum macrocell configuration.
6 atf1504asv(l) 1409i ? pld ? 2/03 or/xor/cascade logic the atf1504asv(l) ? s logic structure is designed to efficiently support all types of logic. within a single macrocell, all the product terms can be routed to the or gate, creating a 5-input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. the macrocell ? s xor gate allows efficient implementation of compare and arithmetic functions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high- or low-level. for combinatorial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimization of product terms. the xor gate is also used to emulate t- and jk-type flip-flops. flip-flop the atf1504asv(l) ? s flip-flop has very flexible data and control functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (this feature is automatically imple- mented by the fitter software). in addition to d, t, jk and sr operation, the flip-flop can also be configured as a flow-through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. the clock itself can either be one of the global clk signal (gck[0 : 2]) or an individual product term. the flip-flop changes state on the clock ? s rising edge. when the gck sig- nal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop ? s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchronous preset (ap) can be a product term or always off. extra feedback the atf1504asv(l) macrocell output can be selected as registered or combinatorial. the extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (this enhancement function is automatically implemented by the fitter software.) feedback of a buried com- binatorial output allows the creation of a second latch within a macrocell. i/o control the output enable multiplexer (moe) controls the output enable signal. each i/o can be individually configured as an input, output or for bi-directional operation. the output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the i/o pins, or a subset of the i/o macrocells. this selection is automatically done by the fitter software when the i/o is configured as an input, all mac- rocell resources are still available, including the buried feedback, expander and cascade logic. global bus/switch matrix the global bus contains all input and i/o pin signals as well as the buried feedback sig- nal from all 64 macrocells. the switch matrix in each logic block receives as its inputs all signals from the global bus. under software control, up to 40 of these signals can be selected as inputs to the logic block. foldback bus each macrocell also generates a foldback product term. this signal goes to the regional bus and is available to four macrocells. the foldback is an inverse polarity of one of the macrocell ? s product terms. the four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay.
7 atf1504asv(l) 1409i ? pld ? 2/03 figure 1. atf1504asv(l) macrocell programmable pin-keeper option for inputs and i/os the atf1504asv(l) offers the option of programming all input and i/o pins so that pin keeper circuits can be utilized. when any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. this cir- cuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption.
8 atf1504asv(l) 1409i ? pld ? 2/03 input diagram i/o diagram speed/power management the atf1504asv(l) has several built-in speed and power management features. the atf1504asv(l) contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. this not only reduces power con- sumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 5 mhz. this feature may be selected as a device option. to further reduce power, each atf1504asv(l) macrocell has a reduced-power bit fea- ture. this feature allows individual macrocells to be configured for maximum power savings. this feature may be selected as a design option. all atf1504asv(l) also have an optional power-down mode. in this mode, current drops to below 5 ma. when the power-down option is selected, either pd1 or pd2 pins (or both) can be used to power down the part. the power-down option is selected in the design source file. when enabled, the device goes into power down when either pd1 or pd2 is high. in the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. all pin transitions are ignored until the pd pin is brought low. when the power-down fea- ture is enabled, the pd1 or pd2 pin cannot be used as a logic input or output. however, the pin ? s macrocell may still be used to generate buried foldback and cascade logic signals.
9 atf1504asv(l) 1409i ? pld ? 2/03 all power-down ac characteristic parameters are computed from external input or i/o pins, with reduced-power bit turned on. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t rpa , must be added to the ac parameters, which include the data paths t lad , t lac , t ic , t acl , t ach and t sexp . the atf1504asv(l) macrocell also has an option whereby the power can be reduced on a per macrocell basis. by enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reducing the overall power con- sumption of the device. each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching, and may be specified as fast switching in the design file. design software support atf1504asv(l) designs are supported by several industry standard third party tools. automated fitters allow logic synthesis using a variety of high-level description lan- guages and formats. power-up reset the atf1504asv is designed with a power-up reset, a feature critical for state machine initialization. at a point delayed slightly from v cc crossing v rst , all registers will be ini- tialized, and the state of each output will depend on the polarity of its buffer. however, due to the asynchronous nature of reset and uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. the clock must remain stable during t d . the atf1504asv has two options for the hysteresis about the reset level, v rst , small and large. to ensure a robust operating environment in applications where the device is operated near 3.0v, atmel recommends that during the fitting process users configure the device with the power-up reset hysteresis set to large. for conversions, atmel pof2jed users should include the flag ? -power_reset ? on the command line after ? file- name.pof ? . to allow the registers to be properly reinitialized with the large hysteresis option selected, the following condition is added: 4. if v cc falls below 2.0v, it must shut off completely before the device is turned on again. when the large hysteresis option is active, i cc is reduced by several hundred micro- amps as well. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf1504asv(l) fuse patterns. once programmed, fuse verify is inhibited. however, the 16-bit user signature remains accessible.
10 atf1504asv(l) 1409i ? pld ? 2/03 programming atf1504asv(l) devices are in-system programmable (isp) devices utilizing the 4-pin jtag protocol. this capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes. atmel provides isp hardware and software to allow programming of the atf1504asv(l) via the pc. isp is performed by using either a download cable, a com- parable board tester or a simple microprocessor interface. to facilitate isp programming by the automated test equipment (ate) vendors. serial vector format (svf) files can be created by atmel provided software utilities. atf1504asv(l) devices can also be programmed using standard third-party program- mers. with third-party programmer the jtag isp port can be disabled thereby allowing four additional i/o pins to be used for logic. contact your local atmel representatives or atmel pld applications for details. isp programming protection the atf1504asv(l) has a special feature that locks the device and prevents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a condition. in addition the pin keeper option preserves the former state during device programming, if this circuit were previ- ously programmed on the device. this prevents disturbing the operation of other circuits in the system while the atf1504asv(l) is being programmed via isp. all atf1504asv(l) devices are initially shipped in the erased state thereby making them ready to use for isp. note: for more information refer to the ? designing for in-system programmability with atmel cplds ? application note.
11 atf1504asv(l) 1409i ? pld ? 2/03 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. when microcell reduced-power feature is enabled. note: typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. dc and ac operating conditions commercial industrial operating temperature (ambient)) 0 c - 70 c-40 c - 85 c v cc (3.3v) power supply 3.0v - 3.6v 3.0v - 3.6v dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 210 i oz tri-state output off-state current v o = v cc or gnd -40 40 ? i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 60 ma ind. 75 ma ? l ? mode com. 5 a ind. 5 a i cc2 power supply current, power-down mode v cc = max v in = 0, v cc ? pd ? mode 0.1 5 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std power com 40 ma ind 55 v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio + 0.3 v v ol output low voltage (ttl) v in = v ih or v il v ccio = min, i ol = 8 ma com. 0.45 v ind. 0.45 output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage - 3.3v (ttl) v in = v ih or v il v ccio = min, i oh = -2.0 ma 2.4 v output high voltage - 3.3v (cmos) v in = v ih or v il v ccio = min, i oh = -0.1 ma v ccio - 0.2 v pin capacitance typ max units conditions c in 8pfv in = 0v; f = 1.0 mhz c i/o 8pfv out = 0v; f = 1.0 mhz
12 atf1504asv(l) 1409i ? pld ? 2/03 timing model absolute maximum ratings* temperature under bias.................................. -40 c to +85 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. max- imum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) input delay t in switch matrix t uim foldback term delay t sexp register control delay t lac t ic t en logic array delay t lad global control delay t glob internal output enable delay t ioe cascade logic delay t pexp fast input delay t fin register delay t su t h t pre t clr t rd t comb t fsu t fh output delay t od1 t od2 t od3 t xz t zx1 t zx2 t zx3 i/o delay t io
13 atf1504asv(l) 1409i ? pld ? 2/03 ac characteristics symbol parameter -15 -20 units min max min max t pd1 input or feedback to non-registered output 3 15 20 ns t pd2 i/o input or feedback to non-registered feedback 3 12 16 ns t su global clock setup time 11 13.5 ns t h global clock hold time 0 0 ns t fsu global clock setup time of fast input 3 3 ns t fh global clock hold time of fast input 1.0 2 mhz t cop global clock to output delay 9 12 ns t ch global clock high time 5 6 ns t cl global clock low time 5 6 ns t asu array clock setup time 5 7 ns t ah array clock hold time 4 4 ns t acop array clock output delay 15 18.5 ns t ach array clock high time 6 8 ns t acl array clock low time 6 8 ns t cnt minimum clock global period 13 17 ns f cnt maximum internal global clock frequency 76.9 66 mhz t acnt minimum array clock period 13 17 ns f acnt maximum internal array clock frequency 76.9 58.8 mhz f max maximum clock frequency 100 83.3 mhz t in input pad and buffer delay 2 2.5 ns t io i/o input pad and buffer delay 2 2.5 ns t fin fast input delay 2 2 ns t sexp foldback term delay 8 10 ns t pexp cascade logic delay 1 1 ns t lad logic array delay 6 8 ns t lac logic control delay 3.5 4.5 ns t ioe internal output enable delay 3 3 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35 pf) 34ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 34ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35 pf) 56ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5.0v; c l = 35 pf) 79ns
14 atf1504asv(l) 1409i ? pld ? 2/03 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac ,t tic , t acl , and t sexp parameters for macrocells running in the reduced- power mode. 3. see ordering information for valid part numbers. input test waveforms and measurement levels t r , t f = 1.5 ns typical output ac test loads t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 79ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5.0v/3.3v; c l = 35 pf) 10 11 ns t xz output buffer disable delay (c l = 5 pf) 6 7 ns t su register setup time 5 6 ns t h register hold time 4 5 ns t fsu register setup time of fast input 2 2 ns t fh register hold time of fast input 2 2 ns t rd register delay 2 2.5 ns t comb combinatorial delay 2 3 ns t ic array clock delay 6 7 ns t en register enable time 6 7 ns t glob global control delay 2 3 ns t pre register preset time 4 5 ns t clr register clear time 4 5 ns t uim switch matrix delay 2 2.5 ns t rpa reduced-power adder (2) 10 13 ns ac characteristics (continued) symbol parameter -15 -20 units min max min max r1 = 703 ? 3.0v output pin cl = 35 pf r2 = 8060 ?
15 atf1504asv(l) 1409i ? pld ? 2/03 power-down mode the atf1504asv(l) includes an optional pin-controlled power-down feature. when this mode is enabled, the pd pin acts as the power-down pin. when the pd pin is high, the device supply current is reduced to less than 3 ma. during power down, all output data and internal logic states are latched internally and held. therefore, all registered and combinatorial output data remain valid. any outputs that were in a high-z state at the onset will remain at high-z. during power down, all input signals except the power-down pin are blocked. input and i/o hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. the power-down mode feature is enabled in the logic design file or as a fitted or translated s/w option. designs using the power-down pin may not use the pd pin as a logic array input. however, all other pd pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. 3. includes t rpa for reduced-power bit enabled. power down ac characteristics (1)(2) symbol parameter -15 -20 units min max min max t ivdh valid i, i/o before pd high 15 20 ns t gvdh valid oe (2) before pd high 15 20 ns t cvdh valid clock (2) before pd high 15 20 ns t dhix i, i/o don ? t care after pd high 25 30 ns t dhgx oe (2) don ? t care after pd high 25 30 ns t dhcx clock (2) don ? t care after pd high 25 30 ns t dliv pd low to valid i, i/o 1 1 s t dlgv pd low to valid oe (pin or term) 1 1 s t dlcv pd low to valid clock (pin or term) 1 1 s t dlov pd low to valid output 1 1 s
16 atf1504asv(l) 1409i ? pld ? 2/03 jtag-bst/isp overview the jtag boundary-scan testing is controlled by the test access port (tap) controller in the atf1504asv(l). the boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing. the atf1504asv(l) does not currently include a test reset (trst) input pin because the tap controller is automatically reset at power-up. the five jtag modes supported include: sample/preload, extest, bypass, idcode and highz. the atf1504asv(l) ? s isp can be fully described using jtag ? s bsdl as described in ieee standard 1149.1b. this allows atf1504asv(l) program- ming to be described and implemented using any one of the third-party development tools supporting this standard. the atf1504asv(l) has the option of using four jtag-standard i/o pins for boundary- scan testing (bst) and in-system programming (isp) purposes. the atf1504asv(l) is programmable through the four jtag pins using the ieee standard jtag programming protocol established by ieee standard 1149.1 using 5v ttl-level programming signals from the isp interface for in-system programming. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are avail- able as i/o pins. jtag boundary-scan cell (bsc) testing the atf1504asv(l) contains up to 68 i/o pins and four input pins, depending on the device type and package type selected. each input pin and i/o pin has its own bound- ary-scan cell (bsc) in order to support boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan regis- ters and up to two update registers. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the capture registers. input to the capture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are generated internally by the jtag tap controller. the bsc configuration for the input and i/o pins and macrocells are shown below. bsc configuration for input and i/o pins (except jtag tap pins) note: the atf1504asv(l) has pull-up option on tms and tdi pins. this feature is selected as a design option.
17 atf1504asv(l) 1409i ? pld ? 2/03 bsc configuration for macrocell 0 1 dq 0 1 0 1 dq dq capture dr capture dr update dr 0 1 0 1 dq dq tdi tdi outj oej shift shift clock clock mode tdo tdo pin bsc macrocell bsc pin pin
18 atf1504asv(l) 1409i ? pld ? 2/03 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gnd ground pins vcc vcc pins for the device atf1504asv dedicated pinouts dedicated pin 44-lead tqfp 44-lead j-lead 68-lead j-lead 84-lead j-lead 100-lead pqfp 100-lead tqfp input/oe2/gclk2 40 2 2 2 92 90 input/gclr 39 1 1 1 91 89 input/oe1 384468849088 input/gclk1374367838987 i/o /gclk3 35 41 65 81 87 85 i/o / pd (1,2) 5, 19 11, 25 17, 37 20, 46 14, 44 12, 42 i/o / tdi (jtag) 1 7 12 14 6 4 i/o / tms (jtag)7 1319231715 i/o / tck (jtag) 26 32 50 62 64 62 i/o / tdo (jtag) 32 38 57 71 75 73 gnd 4, 16, 24, 36 10, 22, 30, 42 6, 16, 26, 34, 38, 48, 58, 66 7, 19, 32, 42, 47, 59, 72, 82 13, 28, 40, 45, 61, 76, 88, 97 11, 26, 38, 43, 59, 74, 86, 95 v cc 9, 17, 29, 41 3, 15, 23, 35 3, 11, 21, 31, 35, 43, 53, 63 3,13, 26, 38, 43, 53, 66, 78 5, 20, 36, 41, 53, 68, 84, 93 3, 18, 34, 39, 51, 66, 82, 91 n/c ???? 1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 # of signal pins 36 36 52 68 68 68 # user i/o pins 32 32 48 64 64 64
19 atf1504asv(l) 1409i ? pld ? 2/03 atf1504asv i/o pinouts mc plc 44-lead plcc 44-lead tqfp 68-lead plcc 84-lead plcc 100- lead pqfp 100- lead tqfp mc plc 44-lead plcc 44-lead tqfp 68-lead plcc 84-lead plcc 100- lead pqfp 100- lead tqfp 1 a 12 6 18 22 16 14 33 c 24 18 36 44 42 40 2 a - - - 21151334 c - - - 454341 3 a/ pd1 11 5 1720141235 c/ pd2 25 19 37 46 44 42 4 a 9 3 15 18 12 10 36 c 26 20 39 48 46 44 5 a 8 2 14 17 11 9 37 c 27 21 40 49 47 45 6 a - - 13 16 10 8 38 c - - 41 50 48 46 7a - - - 158 639c - - - 514947 8/ tdi a 7 1 12 14 6 4 40 c 28 22 42 52 50 48 9 a - - 10 12 4 100 41 c 29 23 44 54 54 52 10a---1139942c---555654 11 a 6 44 9 10 100 98 43 c - - 45 56 58 56 12 a - - 8 9 99 97 44 c - - 46 57 59 57 13 a - - 7 8 98 96 45 c - - 47 58 60 58 14 a 5 43 5 6 96 94 46 c 31 25 49 60 62 60 15a - - - 5 959347 c - - - 616361 16 a 4 42 4 4 94 92 48/ tck c 322650626462 17 b 21 15 33 41 39 37 49 d 33 27 51 63 65 63 18 b - - - 40 38 36 50 d - - - 64 66 64 19 b 20 14 32 39 37 35 51 d 34 28 52 65 67 65 20 b 19 13 30 37 35 33 52 d 36 30 54 67 69 67 21 b 18 12 29 36 34 32 53 d 37 31 55 68 70 68 22 b - - 28 35 33 31 54 d - - 56 69 71 69 23 b - - - 34 32 30 55 d - - - 70 73 71 24b 171127333129 56/ tdo d 383257717573 25 b 16 10 25 31 27 25 57 d 39 33 59 73 77 75 26 b - - - 30 25 23 58 d - - - 74 78 76 27 b - - 24 29 23 21 59 d - - 60 75 81 79 28 b - - 23 28 22 20 60 d - - 61 76 82 80 29 b - - 22 27 21 19 61 d - - 62 77 83 81 30 b 14 8 20 25 19 17 62 d 40 34 64 79 85 83 31 b - - - 24 18 16 63 d - - - 80 86 84 32/ tms b 13 7 1923171564 d/ gclk3 41 35 65 81 87 85
20 atf1504asv(l) 1409i ? pld ? 2/03 supply current vs. supply voltage (t a = 25 c, f = 0) 0 25 50 75 100 2.50 2.75 3.00 3.25 3.50 3.75 4.00 supply voltage (v) i cc (ma) standard power reduced power mode supply current vs. supply voltage pin-controlled power-down mode (t a = 25 c, f = 0) 400 500 600 700 800 2.50 2.75 3.00 3.25 3.50 3.75 4.00 supply voltage (v) i cc (ua) standard & reduced power mode supply current vs. frequency standard power (t a = 25 c) 0.0 25.0 50.0 75.0 100.0 125.0 150.0 0.00 20.00 40.00 60.00 80.00 100.00 frequency (mhz) i cc (ma) standard power reduced power mode supply current vs. supply voltage low-power ("l") version (t a = 25 c, f = 0) 0 5 10 15 20 25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 supply voltage (v) i cc (ua) supply current vs. frequency low-power ("l") version (t a = 25 c) 0.0 20.0 40.0 60.0 80.0 100.0 0.00 5.00 10.00 15.00 20.00 frequency (mhz) i cc (ma) standard power reduced power output source current vs. supply voltage (v oh = 2.4v, t a = 25 c) -16 -14 -12 -10 -8 -6 -4 -2 0 2.75 3.00 3.25 3.50 3.75 4.00 supply voltage (v) i oh (ma) output source current vs. output voltage (v cc = 3.3v, t a = 25 c) -70 -60 -50 -40 -30 -20 -10 0 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output voltage (v) i oh (ma) output sink current vs. supply voltage (v ol = 0.5v, t a = 25 c) 20 25 30 35 40 2.75 3.00 3.25 3.50 3.75 4.00 supply voltage (v) i ol (ma)
21 atf1504asv(l) 1409i ? pld ? 2/03 output sink current vs. output voltage (v cc = 3.3v, t a = 25 c) 0 20 40 60 80 100 0 0.5 1 1.5 2 2.5 3 3.5 4 output voltage (v) i ol (ma) input clamp current vs. input voltage (v cc = 3.3v, t a = 25 c) -100 -80 -60 -40 -20 0 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 input voltage (v) input current (ma) input current vs. input voltage (v cc = 3.3v, t a = 25 c) -10 -5 0 5 10 15 00.511.522.533.5 input voltage (v) input current (ua)
22 atf1504asv(l) 1409i ? pld ? 2/03 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use com- mercial product for industrial temperature ranges, de-rate i cc by 15%. atf1504asv(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 15 8 100 atf1504asv-15 ac44 atf1504asv-15 jc44 atf1504asv-15 jc68 atf1504asv-15 jc84 atf1504asv-15 qc100 atf1500asv-15 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 15 8 100 atf1504asv-15 ai44 atf1504asv-15 ji44 atf1504asv-15 ji68 atf1504asv-15 ji84 atf1504asv-15 qi100 atf1504asv-15 ai100 44a 44j 68j 84j 100q1 100a industrial (-40 c to +85 c) 20 12 83.3 atf1504asvl-20 ac44 atf1504asvl-20 jc44 atf1504asvl-20 jc68 atf1504asvl-20 jc84 atf1504asvl-20 qc100 atf1504asvl-20 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 20 12 83.3 atf1504asvl-20 ai44 atf1504asvl-20 ji44 atf1504asvl-20 ji68 atf1504asvl-20 ji84 atf1504asvl-20 qi100 atf1504asvl-20 ai100 44a 44j 68j 84j 100q1 100a industrial (-40 c to +85 c)
23 atf1504asv(l) 1409i ? pld ? 2/03 packaging information 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
24 atf1504asv(l) 1409i pld 2/03 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 17.399 17.653 d1 16.510 16.662 note 2 e 17.399 17.653 e1 16.510 16.662 note 2 d2/e2 14.986 16.002 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45 ? pin no. 1 identifier 1.14(0.045) x 45 ? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 ? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
25 atf1504asv(l) 1409i pld 2/03 68j ? plcc 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 68j , 68-lead, plastic j-leaded chip carrier (plcc) b 68j 10/04/01 1.14(0.045) x 45 ? pin no. 1 identifier 1.14(0.045) x 45 ? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 ? max (3x) a a1 b1 d2/e2 b e e1 e d1 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-018, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 25.019 25.273 d1 24.130 24.333 note 2 e 25.019 25.273 e1 24.130 24.333 note 2 d2/e2 22.606 23.622 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ
26 atf1504asv(l) 1409i pld 2/03 84j ? plcc 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 84j , 84-lead, plastic j-leaded chip carrier (plcc) b 84j 10/04/01 1.14(0.045) x 45 ? pin no. 1 identifier 1.14(0.045) x 45 ? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 ? max (3x) a a1 b1 d2/e2 b e e1 e d1 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-018, variation af. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 30.099 30.353 d1 29.210 29.413 note 2 e 30.099 30.353 e1 29.210 29.413 note 2 d2/e2 27.686 28.702 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ
27 atf1504asv(l) 1409i pld 2/03 100q1 ? pqfp pin 1 id 16.95 (0.667) 17.45 (0.687) 19.90 (0.783) 20.10 (0.791) 22.95 (0.904) 23.45 (0.923) 0.65 (0.0256) bsc 0.22 (0.009) 0.40 (0.016) 3.40 (0.134) max 0.50 (0.020) 0.73 (0.029) 1.03 (0.041) 13.90 (0.547) 14.12 (0.556) 0.11 (0.004) 0.23 (0.009) 0 ~7 0.25 (0.010) dimensions in millimeters and (inches)* *controlling dimensions: millimeters jedec standard ms-022, gc-1 pin 1 04/11/2001 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100q1 , 100-lead, 14 x 20 mm body, 3.2 mm footprint, 0.65 mm pitch, plastic quad flat package (pqfp) a 100q1
28 atf1504asv(l) 1409i pld 2/03 100a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pin 1 identifier 0 ? ~7 ? pin 1 l c a1 a2 a d1 d e e1 e b a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.17 0.27 c 0.09 0.20 l 0.45 0.75 e 0.50 typ notes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note
printed on recycled paper. 1409i pld 2/03 xm ? atmel corporation 2003. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company s standard warranty which is detailed in atmel s terms and conditions located on the company s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com atmel is the registered trademark of atmel. other terms and product names may be the trademarks of others.

▲Up To Search▲

Price & Availability of ATF1504ASV-15QC100

	To Download ATF1504ASV-15QC100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .